Introduction

Although the official SystemRDL spec defines numerous properties that allow you to define complex register map structures, sometimes they are not enough to accurately describe a necessary feature. Fortunately the SystemRDL spec allows the language to be extended using “User Defined Properties” (UDPs). The PeakRDL-etana tool understands several UDPs that are described in this section.

To enable these UDPs, compile this RDL file prior to the rest of your design: etana_udps.rdl.

Summary of UDPs

Name	Component	Type	Description
buffer_reads	reg	boolean	If set, reads from the register are double-buffered. See: Read-buffered Registers.
rbuffer_trigger	reg	reference	Defines the buffered read load trigger. See: Read-buffered Registers.
buffer_writes	reg	boolean	If set, writes to the register are double-buffered. See: Write-buffered Registers.
wbuffer_trigger	reg	reference	Defines the buffered write commit trigger. See: Write-buffered Registers.
rd_swacc	field	boolean	Enables an output strobe that is asserted on sw reads. See: Read/Write-specific swacc.
wr_swacc	field	boolean	Enables an output strobe that is asserted on sw writes. See: Read/Write-specific swacc.
verilog_reg_only	reg	boolean	If set, the register’s hardware interface signals are grouped as a single vector at the top level instead of individual field signals. Internally, the vector is automatically broken up into the individual fields. See: Vectorized Register Interface.
err_support	mem	boolean	If set on an external memory, adds rd_err and wr_err input ports and propagates errors to the CPU interface (e.g., APB pslverr, AHB hresp). See: External Memory Error Support.