Hardware Interface Reports

PeakRDL-etana can generate comprehensive reports mapping RDL register definitions to the generated flattened signal names.

Overview

The --hwif-report flag generates two report formats:

Markdown ({module}_hwif.rpt) - Human-readable table
CSV ({module}_hwif.csv) - Machine-readable data

These reports provide traceability between RDL definitions and generated signals, including addresses, widths, access types, and reset values.

Generated Files

When using --hwif-report, the following additional files are generated:

{module_name}_hwif.rpt - Markdown table report
{module_name}_hwif.csv - CSV data export

Markdown Report Format

The markdown report contains a formatted table with signal information:

# Hardware Interface Report: pmbus_apb4
Generated from: PMBUS

## Input Signals (to register block)

| Signal Name | Width | RDL Path | Address | SW Access | HW Access | Reset |
|-------------|-------|----------|---------|-----------|-----------|-------|
| `i_page` | [7:0] | PMBUS.PAGE.PAGE | 0x00000004 | r | w | N/A |

## Output Signals (from register block)

| Signal Name | Width | RDL Path | Address | SW Access | HW Access | Reset |
|-------------|-------|----------|---------|-----------|-----------|-------|
| `o_capability_enable` | [0:0] | PMBUS.CAPABILITY.enable | 0x00000000 | rw | r | 0x1 |

## Summary

- Total Input Signals: 1
- Total Output Signals: 8
- Total Signals: 9

CSV Report Format

The CSV report provides machine-readable data for tool integration:

signal_name,direction,width,rdl_path,address,sw_access,hw_access,reset_value
i_page,input,8,PMBUS.PAGE.PAGE,0x00000004,r,w,N/A
o_capability_enable,output,1,PMBUS.CAPABILITY.enable,0x00000000,rw,r,0x1

Column Descriptions

signal_name - Generated signal name (flattened)
direction - input (to register block) or output (from register block)
width - Signal width in bits
rdl_path - Full hierarchical RDL path to field
address - Register address in hexadecimal
sw_access - Software access type (r, w, rw)
hw_access - Hardware access type (r, w, rw)
reset_value - Reset value in hexadecimal (N/A if none)

Usage

Enable report generation:

peakrdl etana my_registers.rdl --hwif-report -o output/

Use Cases

Signal Reference

Quick lookup of which signal corresponds to which RDL field:

Open markdown report
Search for RDL path or signal name
See width, address, and access information

Hardware Integration

Map signals to external blocks:

Export CSV to spreadsheet
Cross-reference with hardware design
Generate connection code

Debugging

Verify signal-to-address mapping:

Compare report with memory map
Verify register access patterns
Debug read/write issues

Test Generation

Automated test creation:

Import CSV to test generator
Create stimulus vectors
Verify register functionality

Example: Using CSV for Test Generation

import csv

# Read hwif report
with open('pmbus_apb4_hwif.csv') as f:
    reader = csv.DictReader(f)
    for row in reader:
        signal = row['signal_name']
        width = int(row['width'])
        address = row['address']

        # Generate test case
        print(f"Testing {signal} at {address}, width {width}")

Example: Integration Spreadsheet

Import the CSV into Excel/LibreOffice to:

Track signal connections
Document pin assignments
Plan board layout
Generate connection tables

Difference from PeakRDL-regblock

PeakRDL-regblock (struct-based):

hwif_in.PAGE.PAGE.next[7:0]
hwif_out.CAPABILITY.enable.value

This format documents struct member paths, which don’t apply to etana’s flattened signals.

PeakRDL-etana (flattened):

i_page,input,8,PMBUS.PAGE.PAGE,0x00000004,r,w
o_capability_enable,output,1,PMBUS.CAPABILITY.enable,0x00000000,rw,r

This format shows actual signal names, making it directly useful for integration and debugging.